Screening Reliability Defects in Advanced Technology Nodes
Victor Champac (National Institute for Astrophysics, Optics and Electronics, Mexico)
CMOS IC scaling has provided significant improvements in electronic circuit performance. At the same time test task has become more difficult due to the increase of circuit complexity and the impact of process variations. Significant test effort needs to be devoted in order to catch important defects such as opens and bridge defects. This will allow a better test quality leading to higher product reliability. In this talk, first a test methodology to generate favorable logic conditions at the coupling lines is presented. Furthermore, low voltage testing can increase even more the detection of interconnect open defects. Second, optimal test conditions to improve resistive bridge detection combining Low VDD and Reverse Body Bias (RBB) are analyzed. A Statistical Timing Analysis Framework (STAF) is used to analyze the possibilities of detection of bridge defects using a delay based test. Third, a test technique oriented to detect defects producing Small Delay Defects (SDDs) is presented. These defects are difficult to detect and are an important source of test escapes, which represents a reliability risk. A methodology to detect SDDs in the presence of process variations using delay correlation information between paths of a circuit is presented. Finally, detection of open defects in circuits implemented in advanced FinFET technology is analyzed. The use of complex interconnect structures (MOL), and multi-fin and multi-finger devices in circuits based in FinFET technology pose a challenge to test open defects.